The development of 3D-ICs and heterogeneous chiplets requires significant changes in physical layout tools, impacting the placement of chiplets and signal routing to enhance system performance and reliability. Key challenges include efficient thermal dissipation, as stacking logic chiplets generates significant heat that traditional planar SoC methods cannot handle. EDA vendors are addressing these issues by integrating thermal management into automation tools and considering multi-die integration and high-density interconnects in design flows.
The industry is shifting towards stacked dies due to the increasing cost of planar scaling, making advanced packaging and chiplets essential for improving performance, especially in AI and high-performance computing. Predictions indicate that most server chips and over 50% of client PCs will utilise chiplets by 2025, driving the need for adaptable tools and workflows.
In the place-and-route flow, designers must consider floor-planning, placement, clocking, and routing, with early decisions on materials and connectivity influencing the entire process. Multi-die designs introduce new challenges, including power delivery and thermal management, requiring consideration of interactions across different layers.
Thermal effects are now a critical factor in design, with early integration of thermal planning and simulation essential to avoid costly fixes later. AI is expected to enhance EDA tools, providing predictive intelligence and optimising floor-planning and place-and-route processes based on historical data.
The shift to 3D-ICs and chiplets presents designers with complex technological requirements, including managing high-speed constraints and efficient power delivery. Innovations such as substrate capacitors and hybrid bonding are necessary for advanced designs. While there is still progress to be made, advancements in 3D placement and thermal-aware planning show promise for achieving optimised, automated 3D-IC design flows.
The move to 3D-ICs and chiplets demands new approaches to thermal management, placement, and routing. The integration of AI and early-stage modelling is key to developing efficient and reliable designs, paving the way for optimised and fully automated 3D-IC design processes.
Alphawave IP Group plc (LON:AWE) is a semiconductor IP company focused on providing DSP based, multi-standard connectivity Silicon IP solutions targeting both data processing in the Datacenter and data generation by IoT end devices.
