Alphawave Semi, a global company specialising in high-speed connectivity and compute silicon for technology infrastructure, has introduced the industry’s first 3nm silicon-proven Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP subsystem. This development was achieved through collaboration with TSMC and uses TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology.
The subsystem has been designed to meet the needs of demanding applications like hyperscale data centres, high-performance computing (HPC), and AI. By leveraging TSMC’s 2.5D silicon-interposer-based packaging, this fully integrated and highly adaptable subsystem delivers a bandwidth density of 8 Tbps per mm, while optimising complexity, power efficiency, and latency in I/O.
Supporting a wide range of industry protocols, including PCIe, CXL, AXI-4, AXI-S, CXS, and CHI, this subsystem ensures compatibility within the expanding chiplet ecosystem. A unique feature is its live per-lane health monitoring, which enhances system reliability. Operating at speeds of 24 Gbps, it is designed to meet the high bandwidth requirements essential for advanced D2D connectivity.
Now available after extensive testing, the subsystem underwent thorough validation using silicon samples provided by TSMC. Alphawave Semi rigorously assessed the subsystem against UCIe standards under varied process conditions, including typical, slow, and fast scenarios, while ensuring it performed optimally at targeted voltage and temperature ranges.
The validation process successfully confirmed the readiness of the UCIe IP subsystem for integration into customer SoC designs. This includes testing the D2D link margin, TXIO, and RXIO loopback margins, all crucial for next-generation HPC and AI applications.
Mohit Gupta, Alphawave Semi’s SVP and GM of Custom Silicon and IP, described the silicon validation of the 3nm 24Gbps UCIe subsystem as a major achievement. He highlighted it as a demonstration of Alphawave Semi’s expertise in leveraging TSMC’s 3DFabric ecosystem to create leading connectivity solutions. Gupta also noted that this IP sets a new standard in high-performance connectivity solutions.
Dan Kochpatcharin, Head of Ecosystem and Alliance Management Division at TSMC, praised the collaboration with Alphawave Semi. He explained how their work aligns with TSMC’s Open Innovation Platform (OIP) ecosystem, enabling significant advances in packaging that meet the growing needs of AI and HPC applications. Kochpatcharin also expressed TSMC’s continued commitment to partnering with Alphawave Semi to further develop the 3D IC design ecosystem, aiming to produce faster and more energy-efficient semiconductor designs.
Complying with the latest UCIe Specification Rev 2.0, Alphawave Semi’s UCIe IP subsystem also includes various test and debug features, such as JTAG, BIST, DFT, and Known Good Die (KGD) capabilities.
This new 3nm 24Gbps UCIe IP subsystem with TSMC CoWoS Packaging follows an earlier announcement in February 2024 by Alphawave Semi, confirming that its 3nm UCIe IP subsystem with standard packaging was silicon-proven. Additionally, it builds on the company’s June release of the industry’s first multi-protocol chiplet.
Alphawave IP Group plc (LON:AWE) is a semiconductor IP company focused on providing DSP based, multi-standard connectivity Silicon IP solutions targeting both data processing in the Datacenter and data generation by IoT end devices.
