GammaCORE, developed by Alphawave Semi, is a Universal Chiplet Interconnect Express (UCle™) Die-to-Die Controller IP that implements the latest UCIe 1.1 specification and supports UCIe Streaming protocol applications. This innovation facilitates multi-die applications such as connecting I/O chiplets to a main die, linking accelerator dies to processor dies, enabling multi-die packet processors, and creating multi-die Ethernet switches.
The GammaCORE IP core is composed of the Streaming Protocol Layer, which extends the SoC interface across the UCIe link, and the Adapter Layer, ensuring a reliable end-to-end connection. On the UCIe link side, GammaCORE interfaces with the AresCORE UCIe D2D PHY IP through the RDI interface, while on the system side, it connects to one or multiple internal SoC interfaces.
Alphawave Semi’s Streaming Protocol supports various interfaces including AXI4, AXI-S, TileLink, CXS, CHI, and several proprietary interfaces. It can handle both single-ported and multi-ported configurations. In multi-ported setups, the Streaming Protocol multiplexes multiple SoC interfaces, such as an AXI4 port and a CXS port, into a single UCIe link.
GammaCORE can be integrated with other Alphawave Semi companion IP cores to enable direct connections to customer core logic, such as a NoC port, or to design PCIe®/CXL® I/O chiplets via the KappaCORE IP Core, PCIe I/O chiplets via the PiCORE IP core, and Ethernet I/O chiplets via the OmegaCORE IP core.
UCIe Adapter Features
GammaCORE supports raw-mode operation and is based on the 256B latency-optimized Flit format, aligning with the UCIe 1.1 specification. It includes Flit CRC generation and checking, retry functionality for reliable data transfer, link state management, protocol and parameter negotiation with remote link partners, and runtime link testing using parity.
Streaming Protocol Layer Features
The Streaming Protocol Layer offers low latency and high bandwidth efficiency, transparently extending one or multiple SoC interfaces across the UCIe link. It supports interfaces like AXI4, AXI-S, TileLink, CXS, CHI, and proprietary interfaces, and is flexible and scalable with configurations for any number of ports and channels per port. Additional features include optional clock domain crossing between SoC and UCIe controller clocks, configurable datapath width for specific bandwidth and target clock frequency requirements, per channel flow control extension and buffering, as well as statistics counters and error reporting and handling.
GammaCORE represents a significant advancement in multi-die interconnect technology, providing robust and flexible solutions for complex chiplet configurations and interconnections.
Alphawave IP Group plc (LON:AWE) is a semiconductor IP company focused on providing DSP based, multi-standard connectivity Silicon IP solutions targeting both data processing in the Datacenter and data generation by IoT end devices.
